1 features two regulated outputs primary output 8v 5%; 750ma secondary output 5v 2%; 100ma low dropout voltage on/off control option standby quiescent drain (<2ma) protection features reverse battery 60v peak transient voltage -50v reverse transient short circuit thermal shutdown package options 5 lead to-220 tab (gnd) 1 cs8164 8v/5v low dropout dual regulator with enable cs8164 description block diagram absolute maximum ratings 1v in 2v out1 3 gnd 4 enable 5v out2 december, 2001 - rev. 4 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs8164 is a low dropout, dual 8v/5v linear regulator. the secondary 5v/100ma output is used for powering systems with standby memory. quiescent current drain is less than 2ma when supplying 10ma loads from the standby regulator. in automotive applications, the cs8164 and all regulated circuits are protected from reverse battery installations, as well as high voltage transients. during line transients, such as a 60v load dump, the 750ma output will automat- ically shutdown to protect both internal circuits and the load, while the sec- ondary regulator continues to power any standby load. the on board enable function con- trols the regulator's primary output. when enable is in the low state, the regulator is placed in standby mode where it draws 2ma (typ) quiescent current. the cs8164 is packaged in a 5-lead to-220, with copper tab for connection to a heat sink, if necessary. dc input voltage .............................................................................-0.5v to 26v transient peak voltage (46v load dump) .................................................60v internal power dissipation ..................................................internally limited operating temperature range................................................-40? to +125? junction temperature range...................................................-40? to +150? storage temperature range ....................................................-65? to +150? reverse polarity v out1 input voltage, dc ................................................-18v reverse polarity input voltage, transient ................................................-50v lead temperature soldering wave solder (through hole styles only)..........10 sec. max, 260? peak v in v out2 gnd v out1 enable output current limit + - output current limit over voltage shutdown primary output standby output + - thermal shutdown bandgap reference + -
2 cs8164 parameter test conditions min typ max unit package lead description package lead # lead symbol function 5 lead to-220 1v in supply voltage, usually direct from battery. 2v out1 regulated output 8v, 750ma (typ). 3 gnd ground connection. 4 enable cmos compatible input lead; switches v out1 on and off. when enable is high, v out1 is active. 5v out2 standby output 5v, 100ma (typ); always on. output stage (v out1 ) output voltage, v out1 13v v in 26v, i out1 500ma, 7.6 8.0 8.4 v 13v v in 16v, i out1 750ma 7.6 8.0 8.4 v dropout voltage i out1 = 500ma 0.60 v line regulation 13v v in 16v, i out1 = 5ma 15 80 mv load regulation 5ma i out1 500ma 15 80 mv quiescent current i out1 10ma, no load on standby 3 7 ma i out1 = 500ma, no load on standby 40 100 ma i out1 = 750ma, no load on standby 90 ma ripple rejection f = 120hz 53 db current limit 0.75 1.40 2.50 a long term stability 50 mv/khr output impedance 500ma dc and 10ma rms, 200 m ? 100hz - 10khz thermal shutdown 150 190 ? overvoltage shutdown 26 40 v standby output (v out2 ) output voltage, (v out2 ) 6v v in 26v 4.75 5.00 5.25 v dropout voltage i out2 100ma 0.55 0.70 v line regulation 6v v in 26v 4 50 mv load regulation 1ma i out2 100ma 10 50 mv quiescent current i out2 10ma, -40? t j +125? 2 3 ma v out1 off ripple rejection f = 120hz 66 db current limit 200 ma long term stability 20 mv/khr output impedance 10ma dc and 1ma rms, 100hz - 10khz 1 ? enable function (enable) input enable threshold v out1 off 1.25 0.80 v v out1 on 2.00 1.25 v input enable current v enable v threshold -10 10 a electrical characteristics for v out : v in = 14v, i out = 500ma, -40? t j +150? unless otherwise specified
3 typical performance characteristics cs8164 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 input-output differential voltage (v) output current (ma) 0 200 400 600 800 dropout voltage vs. output current 7 6 5 4 3 2 1 0 -1 -2 input voltage (v) output voltage (v) 8 9 10 11 12 13 -40 -20 0 20 40 60 r l =10 ? output voltage vs. input voltage 7 6 5 4 3 2 1 0 -1 -2 input voltage (v) output voltage (v) -40 -20 0 20 40 60 r l = 500 ? standby output voltage vs. input voltage 20 10 0 -10 -20 3 2 1 0 time ( s) input voltage change (v) output voltage deviation (mv) i out1 = 500ma 0 102030405060 line transient response (v out1 ) 10 time ( s) input voltage change (v) output voltage deviation (mv) 5 0 -5 -10 3 2 1 0 0 1020 3040 5060 line transient response (v out2 )
4 cs8164 typical performance characteristics: continued output current (ma) quiescent current (ma) 120 100 80 60 40 20 0 0 200 400 600 800 i stby =10ma quiescent current vs. output current 150 time ( s) standby load current (ma) standby output voltage deviation (mv) 100 50 0 -50 -100 -150 20 15 10 5 0 0 102030405060 load transient response (v out2 ) ambient temperature ( c) power dissipation (w) 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 infinite heat sink 10 c/w heat sink no heat sink maximum power dissipation (to-220) 150 time ( s) load current (a) output voltage deviation (mv) 100 50 0 -50 -100 -150 0.8 0.6 0.4 0.2 0 0 102030405060 load transient response (v out1 )
5 the cs8164 is equipped with two outputs. the second output is intended for use in systems requiring standby memory circuits. while the high current primary output can be controlled with the enable lead described below, the standby output remains on under all conditions as long as sufficient input voltage is applied to the ic. thus, mem- ory and other circuits powered by this output remain unaf- fected by positive line transients, thermal shutdown, etc. the standby regulator circuit is designed so that the quies- cent current to the ic is very low (<2ma) when the other regulator output is off. in applications where the standby output is not needed, it may be disabled by connecting a resistor from the standby output to the supply voltage. this eliminates the need for a capacitor on the output to prevent unwanted oscilla- tions. the value of the resistor depends upon the mini- mum input voltage expected for a given system. since the standby output is shunted with an internal 6.0v zener, the current through the external resistor should be sufficient standby output cs8164 v in enable v out1 system condition 60v 3v 2.4v 8v 0v turn on load dump low v in line noise, etc. v out2 short circuit thermal shutdown turn off 5v 0v 14v 5v 2.0v 0.8v 14v 26v 31v 8v 8v 2.4v 8v 8v 5v 0v v out2 typical circuit waveform dropout voltage the input-output voltage differential at which the circuit ceases to regulate against further reduction in input volt- age. measured when the output voltage has dropped 100mv from the nominal value obtained at 14v input, dropout voltage is dependent upon load current and junc- tion temperature. input voltage the dc voltage applied to the input terminals with respect to ground. input output differential the voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. line regulation the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation the change in output voltage for a change in load current at constant chip temperature. long term stability output voltage stability under accelerated life-test condi- tions after 1000 hours with maximum rated voltage and junction temperature. output noise voltage the rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. quiescent current the part of the positive input current that does not con- tribute to the positive load current. i.e., the regulator ground lead current. ripple rejection the ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. temperature stability of v out the percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. current limit peak current that can be delivered to the output. definition of terms circuit description
6 cs8164 to bias v out2 up to this point. approximately 60 a will suffice, resulting in a 10k ? external resistor for most appli- cations. unlike the standby regulated output, which must remain on whenever possible, the high current regulated output is fault protected against overvoltage and also incorporates thermal shutdown. if the input voltage rises above approximately 30v (e.g., load dump), this output will automatically shutdown. this protects the internal circuit- ry and enables the ic to survive higher voltage transients than would otherwise be expected. thermal shutdown is effective against die overheating since the high current out- put is the dominant source of power dissipation in the ic. the enable function controls v out1 when enable is high (5v), v out1 is on. when enable is low, v out1 is off. enable high current output circuit description: continued v in v out2 r d 10k ? c3 + v out2 disabling v out2 when it is not needed. c3 is no longer needed. cs8164 c 1 * 0.1 f enable v in v out1 gnd c 3 ** 10 f + + 10 f c 2 ** v out2 test & application circuit application notes notes: * c1 required if regulator is located far from power supply filter. ** c 2 , c 3 required for stability. the output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instabil- ity. the aluminum electrolytic capacitor is the least expen- sive solution, but, if the circuit operates at low tempera- tures (-25? to -40?), both the value and esr of the capacitor will vary considerably. the capacitor manufac- turers data sheet usually provides this information. the value for each output capacitor shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine acceptable values for c 2 and c 3 a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part for each output. step 1: place the completed circuit with the tantalum capacitors of the recommended values in an environmen- tal chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor c 2 will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load on the output under observation. look for oscillations on the output. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. stability considerations
7 cs8164 application notes: continued step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the output at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage condi- tions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger stan- dard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: remove the unit from the environmental chamber and heat the ic with a heat gun. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found for each output, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitors should be less than 50% of the maximum allow- able esr found in step 3 above. repeat steps 1 through 7 with the capacitor on the other output, c 3 . the maximum power dissipation for a dual output regula- tor (figure 1) is: p d(max) = {v in(max) - v out1(min) }i out1(max) + {v in(max) - v out2(min) }i out2(max) +v in(max) i q (1) where: v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current for the applica- tion, i out2(max) is the maximum output current for the applica- tion, and i q is the quiescent current the regulator consumes at i out(max) . figure 1: dual output regulator with key performance parameters labeled. once the value of p d(max) is known, the maximum permis- sible value of r ja can be calculated: r ja = (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja 's less than the calculated value in equation 2 will keep the die temperature below 150?. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja = r jc + r cs + r sa (3) where: r jc = the junction-to-case thermal resistance, r cs = the case-to-heatsink thermal resistance, and r sa = the heatsink-to-ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the inter- face between them. these values appear in heat sink data sheets of heat sink manufacturers. heat sinks 150? - t a p d v in smart regulator v out1 i out1 i in i q control features } v out2 i out2 calculating power dissipation in a dual output linear regulator
8 part number description cs8164yt5 5 lead to-220 straight cs8164ytva5 5 lead to-220 vertical cs8164ytha5 5 lead to-220 horizontal cs8164 ordering information package specification thermal data 5 lead to-220 r jc typ 2.0 ?/w r ja typ 50 c/w package thermal data package dimensions in mm (inches) 5 lead to-220 (t) straight 2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 13.72 (.540) 1.02 (.040) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design 5 lead to-220 (tha) horizontal 0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) typ 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103) 5 lead to-220 (tva) vertical 1.68 (.066) typ 1.70 (.067) 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)
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